Cell replication and redundancy elimination during placement for cycle time optimization

This paper presents a new timing driven approach for cell replication tailored to the practical needs of standard cell layout design. Cell replication methods have been studied extensively in the context of generic partitioning problems. However, until now it has remained unclear what practical benefit can be obtained from this concept in a realistic environment for timing driven layout synthesis. Therefore, this paper presents a timing driven cell replication procedure, demonstrates its incorporation into a standard cell placement and routing tool and examines its benefit on the final circuit performance in comparison with conventional gate or transistor sizing techniques. Furthermore, we demonstrate that cell replication can deteriorate the stuck-at fault testability of circuits and show that stuck-at redundancy elimination must be integrated into the placement procedure. Experimental results demonstrate the usefulness of the proposed methodology and suggest that cell replication should be an integral part of the physical design flow complementing traditional gate sizing techniques

Cycle time optimization by timing driven placement with simultaneous netlist transformations

We present new concepts to integrate logic synthesis and physical design. Our methodology uses general Boolean transformations as known from technology-independent synthesis, and a recursive bi-partitioning placement algorithm. In each partitioning step, the precision of the layout data increases. This allows effective guidance of the logic synthesis operations for cycle time optimization. An additional advantage of our approach is that no complicated layout corrections are needed when the netlist is changed

Code-Disjoint Circuits for Parity Codes

In this paper it is shown how a circuit, given as a netlist of gates, can be transformed into two different types of code-disjoint circuits. A new method for a joint design of the functional circuit, the output parity and the input parity is proposed. Carefully selected internal nodes of the functional circuit are utilized to reduce the necessary area overhead for the design of input and output parities. 1 Introduction The design of self-testing and self-checking circuits is of growing interest now. The outputs of the monitored circuit are elements of an error detecting code; for instance, a parity code or a Berger code [4, 5, 9, 10, 12--14, 17]. The encoded outputs of the self-testing or self-checking circuit are monitored by a (self-testing) code-checker. Internal faults of the monitored circuit or the checker can be detected by this method. To also detect faults at the input lines, code-disjoint circuits have to be used [13]. Both the inputs and the outputs of a code-disjoint circu..

Synthesis of Code-disjoint Combinational Circuits

In this paper it is shown how a circuit, given as a netlist of gates, can be transformed into a code-disjoint circuit. Carefully selected gates of the separately implemented parity bit are utilized for the optimization of the necessary area overhead. 1 Introduction The design of self-testing and self-checking circuits is of growing interest now. The outputs of the monitored circuit are elements of an error detecting code; for instance, a parity code or a Berger code [4, 6, 9--13, 16]. The encoded outputs of the self-testing or self-checking circuit are monitored by a (self-testing) code-checker. Internal faults of the monitored circuit or the checker can be detected by this method. To also detect faults at the input lines, code-disjoint circuits have to be used [12]. Both the inputs and the outputs of a code-disjoint circuit are encoded [3]. As long as no error occurs input codewords are mapped onto output code-words and noncode inputs are mapped onto non-code outputs by a code-disjoi..

CYCLE TIME OPTIMIZATION BY TIMING DRIVEN PLACEMENT WITH SIMULTANEOUS NETLIST TRANSFORMATIONS

We present new concepts to integrate logic synthesis and physical design. Our methodology uses general Boolean transformations as known from technology-independent synthesis, and a recursive bi-partitioning placement algorithm. In each partitioning step, the precision of the layout data increases. This allows effective guidance of the logic synthesis operations for cycle time optimization. An additional advantage of our approach is that no complicated layout corrections are needed when the netlist is changed. 1